1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic products. More particularly, the present invention relates to linewidth control methods when forming patterned layers within microelectronic products.
2. Description of the Related Art
Common in the art of semiconductor product fabrication is the use of complementary metal oxide semiconductor (CMOS) devices formed within and upon semiconductor substrates. CMOS devices, such as CMOS field effect transistor (FET) devices, are generally of interest within semiconductor products insofar as CMOS devices may often be readily fabricated to provide low power consumption circuits within semiconductor products.
While CMOS devices are thus clearly desirable and often essential in the art of semiconductor product fabrication, CMOS devices are nonetheless not entirely without problems.
In that regard, it is often difficult in the art of semiconductor product fabrication to fabricate CMOS devices with optimized performance insofar as CMOS devices are complementary paired devices whose operating characteristics are not necessarily coincidently optimized.
It is thus towards the goal of fabricating CMOS devices with enhanced performance that the present invention is directed.
Various CMOS devices having desirable properties, and methods for fabrication thereof, have been disclosed in the art of semiconductor product fabrication.
Included but not limiting among the CMOS devices and methods are CMOS devices and methods disclosed within: (1) Kim et al., in U.S. Pat. No. 5,567,642 (a method for fabricating a CMOS device which provides a pair of field effect transistor devices with a pair of gate electrodes of differing compositions); (2) Yu et al., in U.S. Pat. No. 7,723,893 (a gate electrode with multiple silicide layers for use within a CMOS device); and (3) Matsumoto, in U.S. Pat. No. 5,877,535 (an additional method for fabricating a CMOS device which provides a pair of field effect transistor devices with a pair of gate electrodes of differing compositions).
Desirable in the art of semiconductor product fabrication are additional methods for fabricating CMOS devices with optimized performance.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for fabricating a CMOS device.
A second object of the present invention is to provide a method in accord with the first object of the invention, wherein the CMOS device is fabricated with optimized performance.
In accord with the objects of the present invention, the present invention provides a method for forming a pair of patterned layers within a microelectronic product.
To practice the method of the invention, there is first provided a substrate having a first region laterally adjacent a second region. There is then formed over the substrate a uniform thickness blanket target layer which covers the first region and the second region. There is then formed over the uniform thickness blanket target layer a first patterned etch mask layer having a first thickness over the first region and a second patterned etch mask layer having a second thickness different from the first thickness over the second region. Finally, there is then etched the blanket target layer to form a first patterned target layer over the first region and a second patterned target layer over the second region. Within the invention, the first thickness and the second thickness are adjusted such as to optimize a first linewidth of the first patterned target layer and a second linewidth of the second patterned target layer.
The invention is particularly applicable to forming a pair of gate electrodes within a pair of field effect transistor devices within a CMOS device.
The invention provides a method for fabricating a CMOS device, wherein the CMOS device is fabricated with optimized performance.
The invention realizes the foregoing object by employing when fabricating a pair of patterned target layers, which may be a pair of gate electrodes within a pair of field effect transistor devices within a CMOS device, a pair of etch mask layers of different thicknesses such that the pair of patterned target layers when etched from a blanket target layer may be formed with different and optimized linewidths absent fabrication or modification of a photomask to realize the same result.